The semiconductor industry continues to yield integrated circuits (ICs) of increasing density in order to reduce their overall required chip space. At the same time, logic circuits continue to increase in speed, via a combination of higher component switching and pipelining techniques that increase the data throughput.
A standard dynamic bus normally operates in accordance with a clock signal CK, as illustrated in FIG. 1. Clock signal CK has two timing phases--an evaluate phase CK1 and a precharge phase CK2. Components connected to the bus are precharged during precharge phase CK2 and evaluate during evaluate phase CK1. This type of bus is known generally as a single-phase dynamic bus. As the name implies, single-phase dynamic busses require that all components connected to the bus precharge and evaluate during identical phases. Accordingly, the actual bandwidth of the bus in relation to the overall bandwidth is reduced in proportion to the portion (typically 50%) of the duty cycle attributable to the precharge phase.
A common technique for increasing the actual bandwidth of the bus is known in the industry as "pipelining". Pipelining techniques take advantage of the down-time spent during the precharge phase of the clock by partitioning a logic circuit into a plurality of logic stages that are clocked using alternate phases of the common clock signal. Accordingly, while one set of alternating logic stages are evaluating during one phase, the other set of alternating logic stages are precharging. On the next phase, the first set of alternating logic stages precharge, while the second set of alternating logic stages evaluate. Each logic stage represents one clock phase. Thus, once the pipeline becomes full (that is, once the initial input data has traveled downstream through each logic stage), valid data is output from the overall logic circuit on each phase of the clock cycle.
Busses that accommodate devices that evaluate on both phases of the clock signal are herein referred to as "bi-phase". A conventional single-bit bi-phase dynamic bus is generally implemented using two independent bus wires, where one wire is dedicated to CK1 and the other is dedicated to CK2, even though CK1 and CK2 are both generated from a common clock signal. A global clock signal CK is passed through a pair of gater devices designed to generate tightly controlled and precisely timed local clock signals CK1 and CK2 for driving local clock loads. CK1 is in phase with CK; CK2 is typically 180.degree. out of phase with CK. In a conventional design, a source latch A and a destination latch X, which by design both talk to the bus on phase CK1, are coupled to the dedicated CK1 bus wire. Similarly, a source latch B and destination latch Y, which by design both talk to the bus on phase CK2, are coupled to an independent dedicated CK2 bus wire. It will be appreciated by those skilled in the art that two independent bus wires are required to accommodate devices that precharge/evaluate on different clock phases. Two independent bus wires are required because if both types of devices were connected to the same bus wire, a drive fight would result each time the bus was precharged for CK1 type devices at the same time CK2-type devices was trying to drive the bus during its evaluate phase. Furthermore, as a result of the drive fight, it would be impossible to transfer data over the bus. Thus, the implementation of a dynamic bi-phase, single-bit bus has heretofore required two independent wires when different devices in the circuit access the bus on both CK1 and CK2 clock phases.
The alternative to using a dynamic bus is to use a tri-state bus. Because tri-state busses do not rely on the different phases of the clock signal to operate, a single-bit tri-state bus can be implemented using a single wire. Tri-state bus drivers and their associated control logic, however, are more complex than dynamic bus drivers, and thus require more chip area to implement. In addition, tri-state busses are slower than dynamic busses.
As described previously, even with today's advanced techniques, a need always exists to push the limits of speed and space. Accordingly, it would be desirable to be able to combine the benefits (i.e., performance and chip area requirement improvements) of a dynamic bus with that of a tri-state bus (i.e., a single-wire implementation). In particular, a need exists for a bi-phase, single-wire dynamic bus.